The use of bump array structures is popular in applications that require low signal loss at high frequency or require a high number of input/output (I/O) pin-outs. A variety of multi-layer substrate packages are typically used with bump array structures. Typically the multi-layer substrate packages can be classified as either high cost and high performance or low cost and low performance. Low performance packages are typically composed of a few conductive layers and route I/O traces directly on top layer of the circuitry as micro-strip line to reduce the number of layers needed for the design. In contrast, high performance packages typically require strip line routing due to density and signal integrity reasons and further require on package decoupling (OPD). On package decoupling requires a ground and/or power line placed on the top layers of the multi-layer substrate package before I/O traces are routed.
Due to the differing locations of the power and ground plane in different types of multi-layer substrate packages, the bump array configuration can typically be optimized for either the high performance package or the low performance package. The typical configuration of the bump array has power and ground net bumps providing a power and ground circuit to the integrated circuit at the periphery of the bump array. For high performance multi-layer substrate packages, the power and ground bumps are usually located in the outer most row of the bump array, which connects to the power and ground plane placed at the two topmost layers of the package to maximize the efficiency of the OPD capacitor. Low performance multi-layer substrate packages typically have a reduced layer count on the packaging substrate compared to a high performance package and do not have OPD. When configuring the bump array structure, the I/O traces fan-out starting from top layer of the multi-layer substrate package to the lower conductive layers of the multi-layer substrate package, such that the bumps supplying power and ground to the integrated circuit are lower priority and are typically routed after the I/O signal layers. In other cases, the low performance multi-layer substrate may not have dedicated layers for power and ground.
To resolve the difficulties satisfying both high end and low end product routing requirements of differing bump array packages implemented with or without OPD capacitors, as well as to be able to route I/O and the power/ground net in different configurations, there is a need to solve the problems of the prior art to provide a method and apparatus for flexible input and output routing using a universal bump array structure.